1. Field of the Invention
The present invention relates to an IC card and, in particular, to an IC card having a monitor timer.
2. Description of the Related Art
The structure of a conventional IC card is shown in FIG. 4. A stop signal output circuit 2 is connected to a CPU 1. A reset receiving circuit 3 and a monitor timer 4 are connected to the stop signal output circuit 2. In addition, this IC card has a data receiving circuit and a data transmitting circuit (not shown) connected to the CPU 1 for respectively receiving and transmitting data between this card and a terminal device (not shown).
In operation, after data from the terminal device is received in the data receiving circuit, it is input to the CPU 1 where a prescribed process is performed. Subsequently, transmission data is transmitted to the terminal device from the data transmitting circuit as required.
Now suppose that a certain failure occurs in an IC card system which includes the terminal device and the IC card and an external reset signal is issued from the terminal device in order to stop the CPU 1. When this external reset signal is received by the reset receiving circuit 3 of the IC card, a reset signal S.sub.1 is output to the stop signal output circuit 2 from the reset receiving circuit 3. The stop signal output circuit 2 then outputs a stop signal S.sub.3 to the CPU 1, causing the CPU 1 to be reset.
The monitor timer 4 connected to the stop signal output circuit 2 measures the time up to the next response after the reception of a data transmission or the like from the terminal device. Monitor timer 4 overflows when there is no next response from the terminal device and a preset time has elapsed. Monitor timer 4 then outputs a reset signal S.sub.2 to the stop signal output circuit 2 to stop the CPU 1. The stop signal output circuit 2 that has received the reset signal S.sub.2 from the monitor timer 4 outputs the stop signal S.sub.3 to the CPU 1 in the same manner as when it receives the reset signal S.sub.1 from the reset receiving circuit 3. As a result, the CPU 1 enters the stopped state.
Since the stop signal output circuit 2 outputs a stop signal S.sub.3 both when it receives the reset signal S.sub.1 from the reset receiving circuit 3 and when it receives the reset signal S.sub.2 from the monitor timer 4, it cannot be determined which reset signal has caused the CPU 1 to be reset.
That is, it is difficult in the conventional IC card to analyze whether, when a failure occurs and the CPU 1 is reset, this reset is caused by the reception of an external reset signal from the terminal device, or by the operation of the monitor timer 4, or whether noise is mixed in and a reset signal is erroneously received in the reset receiving circuit 3. As a result, there exists a problem in that recovery to a normal state takes a great deal of time and effort.